1. Technical Field
The present invention relates to a test substrate manufacturing apparatus, a method for manufacturing a test substrate, and a recording medium. In particular, the present invention relates to a test substrate manufacturing apparatus for manufacturing a test substrate that tests a plurality of devices under test formed on a wafer under test, a method for manufacturing the test substrate, and a recording medium that stores a program causing the test substrate manufacturing apparatus to function.
2. Related Art
For testing semiconductor chips, an apparatus is known that tests pass/fail of each of a plurality of semiconductor chips formed on a semiconductor wafer, as shown in, for example, Japanese Patent Application Publication No. 2002-222839. This apparatus includes a probe card that can be electrically connected to a plurality of semiconductor chips en bloc.
The test apparatus includes a channel corresponding to each terminal of a semiconductor chip. A test circuit is provided for each channel, and the semiconductor chip is tested by the test circuit exchanging signals with each terminal of the semiconductor chip. In order to enable testing of a variety of semiconductor chips, each channel is provided with a general test circuit that can perform a variety of tests. A general test circuit having a variety of functions is relatively large, and so the total area of the test circuits increases when a general test circuit is provided for each channel. As a result, the test substrate on which the general test circuits are formed is housed in a large chassis such as a test head and is electrically connected to the device under test via a cable and probe card, for example.
Usually, when the signal transmission distance between a test circuit and a device under test is great, it is difficult to perform accurate testing of the device under test due to transmission loss. Therefore, in order to decrease the signal transmission distance between the device under test and the test circuit, the test circuit is provided on a probe card or on a substrate adjacent to the probe card. However, the probe card or the substrate adjacent to the probe card has a limited space in which test circuits can be formed, and so it is difficult to provide a general test circuit for each channel.
Furthermore, a BIST circuit can be provided in the device under test to decrease the size of the test circuits. With this technique, however, a circuit that is not used during actual operation is formed in the semiconductor chip, and this decreases the area in the semiconductor chip in which circuits for actual operation can be formed.
Therefore, it is an object of the present invention to provide a test substrate manufacturing apparatus, a method of manufacturing a test substrate, and a program, which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein.